1. Field of the Invention
The present invention relates to a repair circuit of a semiconductor memory device, and more specifically, to a repair circuit comprising an additional unit for preventing a repair operation when a spare cell fails.
2. Description of the Related Art
If even one of a large number of microscopic cells in a dynamic random access memory (DRAM) fails, the device cannot be normally operated as a DRAM. It is uneconomic to discard the entire memory device because of only a few number of the failed cells in the DRAM.
In order to solve this problem, a DRAM comprises a repair circuit for substituting failed cells with extra spare cells to have improved yield.
When an address of failed cells is inputted into the DRAM, the repair circuit renders the spare cells accessed instead of the failed cells. As a result, through having some failed cells, the DRAM can perform a normal operation due to the repair circuit.
FIG. 1 is a circuit diagram illustrating a conventional repair circuit of a semiconductor memory device.
The conventional repair circuit comprises a fuse box unit 10 and a repair control circuit 20. The fuse box 10 outputs a control signal for controlling a repair operation. The repair control circuit 20 substitutes the failed cell with a spare cell in response to the control signal outputted from the fuse box 10.
The fuse box unit 10 includes a precharge unit 11, a fuse unit 12, an address signal input unit 13 and a latch unit 14. The fuse unit 12 is cut when excessive current flows, and has a first terminal connected to the precharge unit 11. The address signal input unit 13 is connected to a second terminal of the fuse unit 12. The latch unit 14 connected to the first terminal of the fuse unit 12 stably outputs a programmed signal when a fuse is programmed.
The precharge unit 11 comprising a PMOS transistor PM1 controlled by a precharge signal PCG precharges the first terminal of the fuse unit 12 by using a power voltage.
The fuse unit 12 comprises a plurality of fuses F1˜F5 connected in series. If an address of a failed cell is inputted in a memory device, a corresponding fuse of the plurality of fuses F1˜F5 is cut. As a result, the fuse unit 12 can prevent the failed cell from being used in read/write oepration.
The address signal input unit 13 comprises NMOS transistors NM1˜NM5 one-to-one controlled by addresses AD1˜AD5.
The latch unit 14 including inverters I1 and I2 connected with a feed-back type latches a potential of a node A, and transmits the latched potential into the repair control circuit 20.
Hereinafter, the operation of the conventional repair circuit is explained.
When a precharge signal PCG having a low level is inputted into a gate of the PMOS transistor PM1 in the precharge unit 11, the PMOS transistor PM1 is driven to apply a voltage VCC to a first terminal of the fuse unit 12. As a result, the first terminal is precharged.
Thereafter, a plurality of address signals AD1˜AD5 are inputted into the address signal input unit 13. If the address signals AD1˜AD5 are those of a normal cell, the potential of the node A becomes at a low level. When the potential of the node A is at the low level, a potential of a node B becomes at a high level. As a result, the repair control circuit 20 is not driven.
On the other hand, if the address signals AD1˜AD5 inputted into the address signal input unit 13 are those of a failed cell, the potential of the node A becomes at a high level. When the potential of the node A is at the high level, the potential of the node B becomes at a low level. As a result, the repair control circuit 20 is driven to substitute the failed cell with a spare cell.
In this way, the conventional repair circuit compares an inputted address with that of a failed cell programmed in a fuse, and substitutes the failed cell with a spare cell when the inputted address is identical with that of the failed cell.
However, when a substituted spare cell fails, the conventional repair circuit re-substitutes a failed cell with the failed spare cell without detecting the failed spare cell.
As a result, the conventional repair circuit continuously substitutes a failed cell not with a new normal spare cell but with a failed spare cell.